The present invention generally relates to multi-chip modules including a plurality of semiconductor chips mounted on a common substrate, and more particularly to a multi-chip module having an improved heat dissipation efficiency.
In order to meet the demand for increased processing speed, recent computers use multi-chip modules in which a plurality of semiconductor chips are mounted on a common substrate that carries thereon a multilayer interconnection structure. Such a multi-chip module is then mounted on a printed circuit board that may be a mother board of a computer.
In such a construction of multi-chip modules, there arises a problem of increased heating due to the mounting of plural semiconductor chips on a common substrate, wherein each of the semiconductor chips causes an increased heating associated with increased integration density and hence increased power consumption. Thus, it is essential to provide a heat dissipation structure for efficient heat dissipation when designing a multi-chip module.
FIG. 1 shows the construction of a conventional multi-chip module 10.
Referring to FIG. 1, the multi-chip module 10 includes an interconnection substrate 11, wherein the interconnection substrate 11 has a lower major surface on which a multilayer interconnection structure 11a is provided, and semiconductor chips 12.sub.-1 and 12.sub.-2 are mounted upon the interconnection structure 11a. Each of the semiconductor chips 12.sub.-1 and 12.sub.-2 carries thereon a number of bonding pads (not shown) connected to respective patterns included in the multilayer interconnection structure 11a by way of bonding wires, and interconnection patterns in the multilayer interconnection structure 11a are connected to respective interconnection leads 14. Further, the semiconductor chips 12.sub.-1 and 12.sub.-2 are encapsulated upon the interconnection structure 11a by a resin package body 13, together with the bonding wires and the interconnection leads 14. Further, the multi-chip module 10 includes a fin-shaped heat sink 15 on the upper major surface of the interconnection substrate 11, and the multi-chip module 10 is mounted upon a mother board 16.
In FIG. 1, it will be noted that the interconnection structure 11a includes thermal via holes 17 provided in correspondence to the region in which the semiconductor chips are mounted for heat dissipation. Thus, the heat in the semiconductor chips 12.sub.-1 and 12.sub.-2 is conducted from the chip to the substrate 11 along the thermal via holes 17 and reaches the heat sink 15 as indicated by arrows 18, wherein the heat sink 15 radiates the heat thus conducted thereto into the environment.
In such a structure of the multi-chip module, the efficiency of heat radiation from the heat sink 15 is restricted by the thermal resistance of the thermal via holes 17 as well as by the thermal resistance of the substrate 11, wherein the contribution of thermal resistance of the thermal via holes 17 is particularly important in view of the fact that one cannot increase the diameter or number of the thermal via holes 17 arbitrarily according to the needs because of the constraint of pattern density of the interconnection patterns in the interconnection structure 11a. In other words, there exists a limit in the reduction of thermal resistance of the thermal via holes 17. Because of this, the conventional multi-chip module 10 of FIG. 1 has suffered from the problem of relatively large thermal resistance. Associated with the problem of large thermal resistance, the conventional multi-chip module also has a problem in that one cannot mount high power semiconductor chips on such a multi-chip module.